// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:12 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_cr_rw_reg.v
//
//  Control Register for read-write values
//
//  Original Author: Chris Jones
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_cr_rw_reg.v $
//    $DateTime: 2014/09/29 10:26:26 $
//    $Revision: #2 $
//
////////////////////////////////////////////////////////////////////////////// 

`include "dwc_e12mp_phy_x4_ns_cr_macros.v"

module dwc_e12mp_phy_x4_ns_pcs_raw_cr_rw_reg
  #(parameter ROM = 0,
    parameter WIDTH = 1,
    parameter [WIDTH-1:0] RST_VAL = 0,
    parameter [WIDTH-1:0] MSK_VAL = 0) (
					
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_rd_data,
output wire [WIDTH-1:0]           cr_val,
input  wire                       cr_sel,
input  wire                       cr_self_clr,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_wr_data,
input  wire                       cr_wr_en,
input  wire                       cr_clk,
input  wire                       cr_rst
);

generate
if (ROM==1) begin: read_only
  assign cr_val = RST_VAL;
end
else begin: read_write
  reg [WIDTH-1:0] cr_val_reg;
  // Register Logic
  //
  always @(posedge cr_clk or posedge cr_rst) begin
    if (cr_rst)
      cr_val_reg <= RST_VAL;
    else if (cr_self_clr)
      // only clear the bit which has the mask bit asserted
      // otherwise keep the current bit value
      cr_val_reg <= (MSK_VAL & RST_VAL) | (~MSK_VAL & cr_val_reg);
    else if (cr_sel && cr_wr_en)
      cr_val_reg <= cr_wr_data[WIDTH-1:0];
  end
  assign cr_val = cr_val_reg;
end
endgenerate

// Read logic - simply use the read-only register module since it has exactly
// the functionality that we need here.
//
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(WIDTH))
 rd_drv (
   .cr_rd_data (cr_rd_data),
   .cr_sel     (cr_sel),
   .cr_val     (cr_val)
);

endmodule
